1. Field of the Invention
The present invention relates to a level shifter for shifting a level of an input signal.
2. Description of the Related Art
In recent years, a level shifter is used in SRAM or flash EEPROM memories or the like so as to apply a negative voltage to a control gate to drive the memory. Such a level shifter outputs an output signal having a varying level which can take a negative value. Such a level shifter is disclosed in Japanese Unexamined Patent Application Publication No. 11-308092 (Patent Document 1) or the like.
FIG. 8 shows a configuration of the level shifter described in Patent Document 1. The level shifter outputs an output signal LO having a negative level in response to an input signal IN when a negative voltage control signal C is supplied and an output signal LO having the same level as that of the input signal IN when the negative voltage control signal C is not supplied. The level shifter comprises a negative voltage generating circuit 90 which outputs a voltage having a negative level or a ground level as a negative voltage signal VB1 in response to the negative voltage control signal C, a pair of transistors (P91, P92) which receive the input signal IN and its inverted input signal INB, a pair of transistors (N91, N92) which receive the negative voltage signal VB1, and transistors P93, P94, N93 and N94. The transistors P93, P94, N93 and N94 are used to reduce the source-drain voltage of each transistor. When the negative voltage signal VB1 is at the ground level, an inverted control signal CB having the L level is supplied to the transistors N93 and N94. When the negative voltage signal VB1 is at the negative level, an inverted control signal CB having the H level is supplied to the transistors N93 and N94. Voltages VA, VB, VC, VD and VE at nodes in the level shifter vary depending on the input signal IN, as shown in FIG. 9. In FIG. 9, “VTP” indicates a threshold voltage of the transistors P93 and P94, and “VTN” indicates a threshold voltage of the transistors N93 and N94.
However, in the conventional level shifter, for example, when the current driving ability of the transistor N93 is small, a rise time Tc of the source voltage VC is longer than a rise time Te of the drain voltage VE in the transistor N93, so that the source-drain voltage is likely to increase. For example, if the source voltage VC has not reached “−VTN” when the drain voltage VE reaches “Vdd”, the maximum value of the source-drain voltage of the transistor N93 exceeds “Vdd+VTN”.
Thus, the breakdown voltage of a transistor needs to be strictly limited (e.g., the maximum value of the source-drain voltage of the transistor needs to be estimated to be large). As a result, the transistor is caused to have a high breakdown voltage. Therefore, an additional process for increasing the breakdown voltage may disadvantageously lead to an increase in cost or an increase in circuit area.